Silicon-on-insulator (SOI) structures are frequently used in CMOS applications.
Such structures comprise, from their useful surface to their base, a thin silicon layer, a buried layer made of a dielectric material that is typically an oxide, for example, SiO2, generally referred to by the acronym BOX (Buried OXide), and a supporting substrate.
To produce such substrates with relatively thin BOX layers, called UTBOX (Ultra-Thin Buried Oxide) SOIs, using the SMARTCUT® process (by way of reminder, this process is described in the article by B. Aspar and A. J. Auberton-Hervé “Silicon Wafer Bonding Technology for VLSI and MEMS applications” edited by S. S. Iyer and A. J. Auberton-Hervé, 2002, INSPEC, London, chapter 3, lines 35-52), which implements a step of direct bonding a donor substrate to a receiver substrate. There are two possible ways of implementing this bonding:
The first approach consists in bonding oxide to silicon (Ox/Si).
In this technique, the “future” buried oxide is carried by only one of the two bonded substrates, the other substrate being covered only with a thin native oxide layer that is about 1 nm in thickness.
This approach may be preferred when fabricating UTBOX substrates, the BOX of which is more than 15 nm in thickness, since it is a simple and inexpensive method. It is optionally supplemented with a plasma surface activation step in order to improve the macroscopic quality of the thin layer transferred and to ensure perfect “closure” of the bonding interface.
The second approach consists in bonding oxide to oxide (Ox/Ox).
In this technique, each of the two bonded wafers carries part of the future buried oxide. This approach may advantageously be implemented when producing UTBOX substrates, the BOX of which is less than 15 nm in thickness, since, under certain conditions, a better transfer quality can be obtained.
In each of the above two bonding configurations, particular care must be taken regarding the bonding interface, on the one hand so as to ensure a high-quality layer transfer using the SMARTCUT® process, and on the other hand to ensure the bonded structure has the electrical and mechanical properties required at the scale of the subsequently fabricated electronic components.
More precisely, and from the macroscopic point of view, the bonding interface must be characterized by the highest possible bonding energy. In the case of bonding with a view to transferring a thin layer using the SMARTCUT® process, this energy must be sufficiently high to guarantee layer transfer with minimal defects at the interface.
The bond is conventionally strengthened by supplying thermal energy, which helps form covalent bonds between the two bonded surfaces.
Bonding energy is a macroscopic property that may be measured using the razor blade method introduced by Maszara (as described in the article “Silicon-on-insulator by wafer bonding: A review” by W. P. Maszara, J. Electrochem. Soc., Vol. 138, No. 1, 1991).
A high bonding energy is a necessary condition for producing UTBOX substrates (“mechanical” closure of the interface), but it does not guarantee that it will be possible to fabricate high-performance electronic components on these substrates.
From the microscopic point of view, the bonding interface must also be characterized by the fact that covalent bonds are formed uniformly over the entire bonding interface.
The bonding interface is then said to have been closed from the microscopic point of view, or indeed to have been stabilized. Thus, there must be no “remnant” of the bonding interface, such as micro- or nanocavities, synonymous with local variations in the electrical behavior of the bonding interface.
The distinction between these macroscopic and microscopic considerations at the bonding interface is described in U.S. Pat. No. 7,863,158.
An effective way of demonstrating the existence of any as yet imperfectly “stabilized” zones is to carry out chemical etching using a Wright Etch solution, which especially contains HF.
In the case of substrates comprising silicon layers and/or one or more thin buried oxide layers, employing Wright Etch solutions is problematic, and as such it is preferred to observe the cross section of the substrates using high-resolution transmission electron microscopy (abbreviated as “TEM”).
The bonding interface is conventionally stabilized by annealing in an oven for 2 h at 1100° C., for an Ox/Si bond, and at 1200° C., for an Ox/Ox bond.
This type of treatment, in addition to being expensive and difficult to implement industrially, causes substantial local damage at the points where the wafer makes contact with the device used to support it in the oven (these defects being called “boat marks”). This long high-temperature treatment also creates regions of high stress, leading to the creation of defects such as slip lines.
For reasons of cost and quality, alternative approaches are being researched, in particular, approaches having lower thermal budgets.
In the case of oxide/silicon bonding, aforementioned U.S. Pat. No. 7,863,158 describes an approach that closes the interface perfectly.
It consists in either carrying out a plasma activation step before the bonding, supplemented with rapid thermal annealing (RTA) at 1200° C. for 30 s post-transfer, or two successive RTA treatments post-transfer, the first being carried out at 1200° C. for 30 s and the second between 1200° C. and 1250° C. for 30 s. This technique, which is appropriate for Ox/Si bonding, indeed makes the distinction between a strong bond (mechanical strength, at the macroscopic scale) and the microscopic aspect (structural stabilization of the bonding interface), the latter aspect being crucial if the components subsequently fabricated on the substrates thus produced are to function correctly.
In the case of oxide/oxide bonding, International Publication No. WO 2010/049496, in the name of the present Applicant, describes the advantage of implementing such bonding to produce UTBOX substrates using the SMARTCUT® technique, but only addresses the macroscopic aspect of the bonding.
In particular a process implementing Ox/Ox bonding is described therein, this process ensuring a high-quality transfer but not ensuring the substrate obtained has an optimal finish and not ensuring complete stabilization of the bonding interface.
Specifically, the conditions of the bonding and of the SMARTCUT® splitting anneal, and the strengthening of the bonding interface are all chosen in order to maximize the transfer quality of the thin layer, but do not allow the bonding interface to be closed from the microscopic point of view while limiting any damage during the finishing heat treatment.
Thus, this document teaches implementing an RTA at between 900° C. and 1300° C. in order to strengthen the bonding interface “macroscopically”, i.e., in order to prevent defects from forming at the bonding interface.
The present inventors, following the teachings of International Publication No. WO 2010/049496 but implementing two successive RTAs, as taught by U.S. Pat. No. 7,863,158, have observed that these anneals do not stabilize the Ox/Ox bonding interface, and therefore the substrates realized in this way do not provide the electrical performance required for microelectronic or optoelectronic applications.
For example, after a finishing step comprising two RTAs at 1200° C. for 30 s, the Ox/Ox bonding interface 22 is still very partially open, as appended FIGS. 2A and 2B show, these figures being TEM micrographs of an interface 22.
Thus, for FIG. 2A, two RTAs were carried out, at the same temperature (1200° C.) and for a length of time of 30 s. For FIG. 2B, the first RTA was carried out at 1200° C. for 30 s, and the second at 1250° C. for the same length of time.
The presence of a large number of nanocavities will be noted, meaning that the formation of covalent bonds between the two bonded surfaces is still incomplete. If a transistor were fabricated above these defective zones, it would perform differently to those produced above stabilized zones, or it might not function at all.